Full Adder Circuit Based on Complementary Energy Path Adiabatic Logic using NAND Gates

Ankitha; Jayalaxmi H

doi:10.48001/jocevd.2023.111-5

Authors

Ankitha Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Jayalaxmi H Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India

DOI:

https://doi.org/10.48001/jocevd.2023.111-5

Keywords:

CMOS (Complementary Metal-Oxide Semiconductor), CEPAL, Energy savings, Full adder, Operating voltage

Abstract

A prospective substitute for conventional CMOS is adiabatic logic, which can be used to build low-power electronics. By ensuring a constant low drop in energy over electrically conductive objects, adiabatic logic architectures reduce energy loss. While all families of adiabatic logic rely on an intermittent ramp voltage source, standard logic in CMOS charges the load capacitance using a constant voltage source. Based on a 1-bit complete adder circuit complementarity in energy paths and adiabatic reasoning was designed virtually and tested experimentally. The suggested cadence in 180nm technology has been simulated investigated, and it has been performing contrasted with that of the traditional whole CMOS circuit. When compared to the conventional The CEPAL-based complete adder circuit, which is based on CMOS technology, displays at a frequency of 100MHz and an operating voltage of 1.8V, there is a 70% energy reduction.

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