Performance Analysis of 8-Bit Carry Select Adder
DOI:
https://doi.org/10.48001/jocevd.2023.116-10Keywords:
Carry-Select Adder (CSA), Fast switching, Low resistance, MTCMOS D-latch, Transistor countAbstract
In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.
Downloads
References
Clapten, J. E., Konguvel, E., & Thangamani, M. (2015). VLSI implementation of low power area efficient fast Carry Select Adder. International Journal of Computer Applications, 115(6).
Dube, A., Sreshta, S., & Singh, D. (2018, September). Design and implementation of dual-pair-single-rail checker with carry select adder. In 2018 2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE) (pp. 224-229). IEEE. https://doi.org/10.1109/ICMETE.2018.00057.
Gaur, N., Mehra, A., Kumar, P., & Kallakuri, S. (2019, March). 16 Bit power efficient carry select adder. In 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) (pp. 558-561). IEEE. https://doi.org/10.1109/SPIN.2019.8711565.
Kaushik, N., & Srinivasu, B. (2023). IMPLY-based high-speed conditional carry and carry select adders for in-memory computing. IEEE Transactions on Nanotechnology, 22, 280-290. https://doi.org/10.1109/TNANO.2023.3284845.
Koyada, B., Meghana, N., Jaleel, M. O., & Jeripotula, P. R. (2017, March). A comparative study on adders. In 2017 International Conference on Wireless Communications, Signal Processing And Networking (WiSPNET) (pp. 2226-2230). IEEE. https://doi.org/10.1109/WiSPNET.2017.8300155.
Kukreti, K., Kumar, P., Barthwal, S., Juyal, A., & Joshi, A. (2021, January). Performance analysis of full adder based on domino logic technique. In 2021 6th International Conference on Inventive Computation Technologies (ICICT) (pp. 312-316). IEEE. https://doi.org/10.1109/ICICT50816.2021.9358544.
Miao, J., & Li, S. (2017, October). A novel implementation of 4-bit carry look-ahead adder. In 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) (pp. 1-2). IEEE. https://doi.org/10.1109/EDSSC.2017.8126457.
Natarajan, P. B., Ghosh, S. K., & Karthik, R. (2017, April). Low power high performance carry select adder. In 2017 International conference of Electronics, Communication and Aerospace Technology (ICECA) (Vol. 2, pp. 601-603). IEEE. https://doi.org/10.1109/ICECA.2017.8212736.
Parmar, S., & Singh, K. P. (2013, February). Design of high speed hybrid carry select adder. In 2013 3rd IEEE International Advance Computing Conference (IACC) (pp. 1656-1663). IEEE. https://doi.org/10.1109/IAdCC.2013.6514477.
Reddy, P. S. K., & Saini, G. (2019, May). Design of carry select adder with online testability using reversible gates. In 2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) (pp. 486-490). IEEE. https://doi.org/10.1109/RTEICT46194.2019.9016873.
Sathyabhama, B., Deepika, M., & Deepthi, S. (2015, April). Area and power efficient carry select adder using 8T full adder. In 2015 International Conference on Communications and Signal Processing (ICCSP) (pp. 0969-0973). IEEE. https://doi.org/10.1109/ICCSP.2015.7322642.
Soundharya, M., & Arunkumar, R. (2015, November). GDI based area delay power efficient carry select adder. In 2015 Online International Conference on Green Engineering and Technologies (IC-GET) (pp. 1-5). IEEE. https://doi.org/10.1109/GET.2015.7453845.
Sreelatha, P., Lakshmi, P. K., & Rao, R. (2017, May). Performance analysis of 1-bit full adder using different design techniques. In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) (pp. 2262-2266). IEEE. https://doi.org/10.1109/RTEICT.2017.8257003.
