Study of Ionization Radiation Effects in Digital Circuits for Aerospace Application

Divyashree N; Chethan R; Mujeeb Ahmed; Bhanu Kiran M S; Jayalaxmi H

doi:10.48001/joeeed.2023.1116-20

Authors

Divyashree N Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Chethan R Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Mujeeb Ahmed Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Bhanu Kiran M S Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Jayalaxmi H Associate Professor, Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India

DOI:

https://doi.org/10.48001/joeeed.2023.1116-20

Keywords:

180nm CMOS technology, Cadence virtuoso, C-element, RHBD (Radiation Hardening-By-Design), SETs (Single Event Transients)

Abstract

Combinational standard cells based on the RHBD approach and using 180 nm technology with Cadence Virtuoso are the focus of this work effort. Radiation from space, heavy ions, and radioactive particles (protons, neutrons) pose the greatest threat to integrated circuits (ICs).Single Event Transients (SETs), a serious issue for digital semiconductor design, are caused by ever reduced feature sizes and declining supply voltage. The three proposed C-element based cells under investigation are inverter, NAND gate, and buffer. The Cadence Virtuoso programme was used to create their schematics. RHBD-based circuit designs are more tolerant of Single Event Effects (SEE), better at resisting noise, and consume less static power. Less static power is used in RHBD-based circuit designs, which also have better noise resistance. For the other C-element-based logic circuits, the Noise Margin is likewise enhanced in comparison to the comparable conventional circuits.

Downloads

Download data is not yet available.

References

Baumann, R. (2005). Soft errors in advanced computer systems. IEEE Design & Test of Computers, 22(3), 258-266. https://doi.org/10.1109/MDT.2005.69.

Mavis, D. G., & Eaton, P. H. (2007, April). SEU and SET modeling and mitigation in deep submicron technologies. In 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual (pp. 293-305). IEEE. https://doi.org/10.1109/RELPHY.2007.369907.

Mohanram, K. (2005, May). Closed-form simulation and robustness models for SEU-tolerant design. In 23rd IEEE VLSI Test Symposium (VTS'05) (pp. 327-333). IEEE. https://doi.org/10.1109/VTS.2005.35.

Shams, M., Ebergen, J. C., & Elmasry, M. I. (1998). Modeling and comparing CMOS implementations of the C-element. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 6(4), 563-567. https://doi.org/10.1109/92.736128.

Toro, D. G., Arzel, M., Seguin, F., & Jezequel, M. (2014). Soft error detection and correction technique for radiation hardening based on C-element and BICS. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(12), 952-956. https://doi.org/10.1109/TCSII.2014.2356911.

Trivedi, R., Devashrayee, N. M., Mehta, U. S., Desai, N. M., & Patel, H. (2015, June). Development of radiation hardened by design (RHBD) primitive gates using 0.18 μm CMOS technology. In 2015 19th International Symposium on VLSI Design and Test (pp. 1-2). IEEE.

https://doi.org/10.1109/ISVDAT.2015.7208046.

Verma, P., Sharma, A. K., Pandey, V. S., Noor, A., & Tanwar, A. (2016). Estimation of leakage power and delay in CMOS circuits using parametric variation. Perspectives in Science, 8, 760-763. https://doi.org/10.1016/j.pisc.2016.06.081.