Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder

Syed Mohsin; Rahul J Gowda; Asha CN; Sumalatha S

doi:10.48001/joeeed.2023.115-9

Authors

Syed Mohsin Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Rahul J Gowda Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Asha CN Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India
Sumalatha S Department of Electronics and Communication Engineering, Acharya Institute of Technology, Bengaluru, Karnataka, India

DOI:

https://doi.org/10.48001/joeeed.2023.115-9

Keywords:

Accumulator unit, Carry look-ahead adder, Carry select adder, Multiplier, Vedic multiplier

Abstract

In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

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