Single Phase Novel H-Type Multilevel Inverter Topology with Optimal Reduction of Power Electronic Devices

Samrat Paul; Sourav Debnath; Dipak Kumar Mandal; Bidyut Mahato

doi:10.52756/ijerr.2023.v36.031

Samrat Paul Department of Electrical and Electronics Engineering, Swami Vivekananda Institute of Science and Technology, Kolkata-700145, West Bengal, India
Sourav Debnath Department of Electrical and Electronics Engineering, Swami Vivekananda Institute of Science and Technology, Kolkata-700145, West Bengal, India https://orcid.org/0000-0001-7583-0381
Dipak Kumar Mandal Department of Applied Physics, Rashbehari Siksha Prangan, University of Calcutta, Kolkata-700009, India
Bidyut Mahato Department of Electrical Engineering, IIT(ISM), Dhanbad, Jharkhand-826004, India

DOI: https://doi.org/10.52756/ijerr.2023.v36.031

Keywords: Generalized structure, H-bridge inverter, Multilevel inverter (MLI), Nearest level control (NLC)

Abstract

The research aims to develop a novel H-Type multilevel inverter capable of generating seventeen levels of asymmetric voltage ratios using only nine power semiconductor switches. The flexibility of this topology is that it can be extended to any desired output levels according to various algorithms suggested in this paper. Simulations are conducted using the MATLAB platform to validate the viability of the proposed topology. The results obtained from these simulations convincingly demonstrate the effectiveness of the designed inverter. Specifically, utilizing the first algorithm, voltage levels of 17, 25, 33 and 41 are generated, and various performance parameters are thoroughly examined to establish the efficacy of the topology. This research not only focuses on the development of a novel H-Type multilevel inverter capable of producing seventeen levels of asymmetric voltage ratios with a minimalistic approach of nine power semiconductor switches but also provides a pathway for extension through suggested algorithms. The validation process through MATLAB simulations and the thorough examination of performance parameters underscores the robustness and efficiency of the proposed topology.

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