A Dynamic Supply Modulator in 18 nm FinFET Node Using Comparator Approach
DOI:
https://doi.org/10.52756/ijerr.2024.v44spl.020Keywords:
3.5GHz, 8-bit comparator, 5G, 18nm FinFET, supply modulatorAbstract
To keep up with the rapid development and to increase spectral efficiency, emerging communication systems like 5G will need to transfer data at speeds significantly faster than those of current systems. The subject of this study is radio frequency (RF) circuit systems, with an emphasis on efficiency enhancement for RF power amplifiers (PA). To cut costs and size, the majority of a smartphone's components are now integrated into a single chip. Regardless of the input signal's magnitude, the fundamental idea behind the envelope tracking (ET) approach is to operate the linear PA in its high-efficiency area. This is achieved by modulating the linear PA's supply voltage, which is as low as 1V, after determining the input signal's magnitude. In view of reducing the chip area and enhancing the efficiency of the PA, an 18nm FinFET node has been used and a comparator-based approach is demonstrated. Keeping the parameters of the 5G specifications in mind, a single-bit comparator is designed to operate at the Sub-6 GHz frequency band with a centre frequency of 3.5 GHz. The propagation delay of the comparator is as low as 67.18ps, and the 8-bit comparator, designed by cascading single-bit comparators, serves as the dynamic power source for the supply modulator. This study provides scope for further development in integrating the comparator with an RF PA for efficiency enhancement. The digital approach of using a comparator instead of bulky circuits provides an upper edge in terms of power consumption and reduction in chip area. The power consumption of the entire efficiency-enhanced PA in an 18nm FinFET technology is expected to reduce considerably in comparison with the CMOS technology.
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